1. Technical Field
The present disclosure relates to data processing systems comprising several elements communicating between themselves through an interconnected network. The present disclosure relates in particular to SoC (System-on-Chip) systems, integrated into a semiconductor chip.
2. Description of the Related Art
Data transmission in a network linking several elements of a processing system, suffers delays due to intrinsic latencies related to the architecture of the network. The sources of such latency are generally found in the routing arrays, the possible format conversion processes applied to the data, and the time required for data to transit in buffer or temporary storage memories. The data sent may also have to undergo specific processes before being received by a receiving element.
FIG. 1 schematically represents a processing system comprising a transmission network TN, initiation elements INIT1, INIT2 capable of initiating a communication in the network, receiving elements TGT1, TGT2 capable of receiving messages from the network, and possibly specific processes PRCA, PRCB likely to be applied to the messages before they are sent to the receiving elements. The global latency for message transmission is equal to the latency Ln of the network increased by the latency Lpi introduced by the process PRCA, PRCB applied to the message.
In a System-on-Chip (SoC), the interconnected network TN is generally a bus, for example of STBus or AMBA type, etc. The initiation elements INIT1, INIT2 are elements which can be master on the bus and initiate transactions towards the receivers. The initiation elements are for example processing units (CPU), and DMA (Direct Memory Access) control units. The receiving elements TGT1, TGT2 are slave elements which can only respond to requests sent by the initiation elements. The receiving elements are for example an external memory of the system and an acceleration unit.
Furthermore, it is often necessary to protect the external memory of a system against attacks aiming to read or change its content. To counter this type of attack, one well-known method involves applying a ciphering function to the data before writing it in the external memory, and a reverse function to the data read in the memory.
Thus, FIG. 2 schematically represents a System-on-Chip PS connected to an external memory EMEM. The system PS comprises initiation units such as a processing unit CPU and a DMA control unit DCU, a bus infrastructure BIS, and a ciphering/deciphering interface unit EDU enabling the data stored in the external memory EMEM to be secured. The bus infrastructure BIS introduces a latency Ln into the sending of requests for accessing the memory EMEM sent by the initiation units CPU. The unit EDU introduces additional latency Lp in the processing of these requests. It shall be noted that the initiation units can also introduce latencies corresponding for example to transit times in a cache memory or a buffer memory. The time needed to access the external memory which can be quite long is also a latency Lm which increases the duration of the process of ciphering or deciphering the data written or read in the memory EMEM.